Timing Driven Multi-FPGA Board Partitioning
نویسندگان
چکیده
System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for architecturally constrained reconngurable multi-FPGA systems. The partitioning approach using a Path-based clustering based on the attraction function proposed by Kahng et.al 19] followed by FM based min-cut partitioning and Re-timing provides a solution for the pin, area and timing constraints of such systems. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on Partitioning benchmark circuits from MCNC and some large scale real designs. The path-based clustering heuristic gives a 5 % improvement in cutset and a 12 % in delay over the FM method on an average. Retiming gives a substantial improvement in clock speed after partitioning.
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